1 ps8546a 07/13/01 gnd2 pciclk_e x2 pciclk0 pciclk1 pciclk_f pciclk2 pciclk3 pciclk4/ sel100/66.6# vdd3 48mhz ref0 ioapic vddla cpuclk1 cpuclk2 vddlc gnd pci_stop# cpu_stop# pd# spread# gnd3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 gnd1 x1 vdd2 cpuclk0 vdd1 pin configuration block diagram description the PI6C106 is part of a reduced pin count two-chip clock solution for designs using an intel bx style chipset. companion sdram buffers are pi6c182 & pi6c184. there are two plls, with the first pll capable of spread spectum operation. cpu frequencies up to 100 mhz are supported. features three cpus @2.5v, up to 100 mhz seven pcis @ 3.3v (including one free running, 1 early) one 48 mhz @ 3.3v fixed one ref (3.3v, 14.318 mhz) one ioapic (2.5v, 14.318 mhz) strong ref clock (1v/ns @50pf load) excellent power management features including power down, pci, and cpu stops spread spectrum for emi control (0.5% down spread) early pci (2.5ns 700ps) enhanced pciclk4 (1.5x) 28-pin ssop packaging (h) 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1 2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pentium/pro tm system clock chip PI6C106 28-pin h frequency table # 6 . 6 6 / 0 0 1 l e sz h m u p cz h m i c p 10 0 13 . 3 3 06 . 6 63 . 3 3 ioapic ref0 vddla x1 x2 cpu_stop# spread# osc pd# sel 100/66.6# pci_stop# cpuclk(0:2) vddlc pciclk_e pciclk_f 48mhz pciclk(0:4) cpu stop bus stop# pll spread spectrum 2 pll2 3
PI6C106 pentium/pro tm system clock chip 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 2 ps8546a 07/13/01 pin descriptions note: inactive means outputs are held low and are disabled from switching r e b m u n n i pe m a n n i pe p y tn o i t p i r c s e d 11 d n gr w p. 2 x , 1 x , t u p t u o f e r r o f d n u o r g 21 xn i k c a b d e e f d n a p a c d a o l f p 3 3 l a n r e t n i s a h , t u p n i l a t s y r c z h m 8 1 3 . 4 1 n i _ l a t x . 2 x m o r f r o t s i s e r 32 xt u of p 3 3 p a c d a o l l a n r e t n i s a h , t u t u o l a t s y r c t u o _ l a t x 42 d n gr w ps t u p t u o i c p r o f d n u o r g 5e _ k l c i c pt u o y b d e t c e f f a t o n . s p 0 5 2 s n 2 y b ) f _ , 4 : 0 ( k l c i c p s d a e l . k l c i c p y l r a e . # p o t s _ i c p 6f _ k l c i c pt u o. # p o t s _ i c p y b d e t c e f f a t o n . t u p t u o i c p g n i n n u r e e r f 1 1 , 0 1 , 8 , 7) 3 : 0 ( k l c i c pt u o. v 3 . 3 e l b i t a p m o c l t t . s t u p t u o k c o l c i c p 92 d d vr w p. v 3 . 3 y l l a n i m o n , s t u p t u o k l c i c p r o f r e w o p 2 1 4 _ k l c i c pt u o) x 5 . 1 ( . v 3 . 3 e l b i t a p m o c l t t . t u p t u o k c o l c i c p # 6 . 6 6 / 0 0 1 l e sn i . z h m 6 . 6 6 r o z h m 0 0 1 g n i l b a n e r o f n i p t c e l e s . ) z h m 3 . 3 3 s u o n o r h c n y s s y a w l a i c p ( z h m 6 . 6 6 = l , z h m 0 0 1 = h 3 13 d d vr w p. z h m 8 4 r o f r e w o p 4 1z h m 8 4t u o. z h m 8 4 @ t u p t u o k l c d e x i f 5 13 d n gr w p. z h m 8 4 r o f d n u o r g 6 1# d a e r p sn i. 1 . 0 d a e r p s n w o d % 5 . 0 . e v i t c a n e h w m u r t c e p s d a e r p s n o s n r u t 7 1# d pn i. f f o d e n r u t e r a t u p t u o l l a , s l l p l a n r e t n i . p i h c n w o d s r e w o p 8 1# p o t s _ u p cn i. w o l s i t u p n i n e h w l e v e l " 0 " c i g o l t a ) 0 : 2 ( k l c u p c s t l a h 9 1# p o t s _ i c pn i e _ k l c i c p t c e f f a t o n s e o d . w o l s i t u p n i n e h w l e v e l " 0 " c i g o l t a ) 4 : 0 ( k l c u p c s t l a h f _ k l c i c p d n a 0 2d n gr w p. e r o c l l p r o f d n u o r g 1 2c l d d vr w pv 5 . 2 y l l a n i m o n , s t u p t u o u p c r o f r e w o p 4 2 , 3 2 , 2 2) 0 : 2 ( k l c u p ct u ov 5 . 2 y l l a n i m o n s t u p t u o k c o l c t s o h d n a u p c 5 2a l d d vr w p. c i p a o i r o f r e w o p 6 2c i p a o it u o. z h m 8 1 3 . 4 1 t u p t u o k c o l c c i p a o i 7 21 d d vr w p. s t u p t u o f e r r o f r e w o p 8 20 f e rt u o. t u p t u o k c o l c z h m 8 1 3 . 4 1
PI6C106 pentium/pro tm system clock chip 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567890123 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567890123 3 ps8546a 07/13/01 cpu_stop# timing diagram cpus_stop# is an asychronous input to the clock synthesizer. it is used to turn off the cpuclks for low power operation. all other clocks will continue to run while the cpuclks clocks are disabled. the cpuclks will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. cpuclk on latency is less than 4 cpuclks and cpuclk off latency is less than 4 cpuclks. notes: 1. all timing is referenced to the internal cpuclk. 2. cpu_stop# is an asynchronous input and metastable conditions may exist. this signal is synchronized to the cpuclks inside pi 6c106. 3. all other clocks continue to run undisturbed including sdramr. 4. pd# and pci_stop# are shown in a high (true) state. notes: 1. all timing is referenced to the internal cpuclk (defined as inside the PI6C106 device.) 2. pci_stop# is an asynchronous input, and metastable conditions may exist. this signal is required to be synchronized inside the PI6C106. 3. all other clocks continue to run undisturbed. 4. pd# and cpu_stop# are shown in a high (true) state. internal cpuclk pciclk (0:4) cpu_stop# pci_stop# (high) pd# (high) cpuclk (0:2) internal cpuclk internal pciclk pciclk (free-runningl) pciclk (external) cpu_stop# pci_stop# pwr_dwn# pci_stop# timing diagram pci_stop# is an asynchronous input to the PI6C106. it is used to turn off the pciclk (0:5) clocks for low power operation. pci_ stop# is synchronized by the PI6C106 internally. pciclk (0:5) clocks are stopped in a low state and started with a full high pulse w idth guaranteed. pciclk (0:5) clock on latency cycles are only one rising pciclk clock off latency is one pciclk clock.
PI6C106 pentium/pro tm system clock chip 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 4 ps8546a 07/13/01 pd# timing diagram the power down selection is used to put the part into a very low power state without turning off the power to the part. pd# is an asynchronous active low input. this signal is synchronized internal by the PI6C106 prior to its control action of powering down the clock synthesizer. internal clocks will not be running after the device is put in power down state. when pd# is active (low) all clocks are driven to a low state and held prior to turning off the vcos and the crystal oscillator. the power on late ncy is guaranteed to be less than 3ms. the power down latency is less than three cpuclk cycles. pci_stop# and cpu_stop# are don?t care signals du ring the power down operations. notes: 1. all timing is referenced to the internal cpuclk (defined as inside the PI6C106 device). 2. pd# is an asynchronous input and metastable conditions may exist. this signal is synchronized inside the PI6C106. 3. the shaded sections on the vco and the crystal signals indicate an active clock is being generated. cpuclk (internal) cpuclk (0:2) pciclk_e, pciclk_f, pciclk (0:4) ref, ioapic internal vcos internal crystal osc. pciclk (internal) pd#
PI6C106 pentium/pro tm system clock chip 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567890123 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567890123 5 ps8546a 07/13/01 supply voltage ........................................................... 7.0 v logic inputs ............................... gnd ?0.5 v to v dd +0.5 v ambient operating temperature .................. 0c to +70c storage temperature ................................ ?65c to +150c electrical characteristics - input/supply/common output parameters t a = 0c - 70c; supply voltage v dd = v ddl = 3.3 v 5% (unless otherwise stated). r e t e m a r a pl o b m y ss n o i t i d n o c. n i m. p y t. x a ms t i n u e g a t l o v h g i h t u p n iv h i 2 v d d - 0 + 3 . v e g a t l o v w o l t u p n iv l i v s s 3 . 0 ?8 . 0 t n e r r u c h g i h t u p n ii h i v n i v = d d 5 a t n e r r u c w o l t u p n ii 1 l i v n i s r o t s i s e r p u - l l u p o n h t i w s t u p n i ; v 0 =5 ? t n e r r u c w o l t u p n ii 2 l i v n i s r o t s i s e r p u - l l u p h t i w s t u p n i ; v 0 =0 0 2 ? g n i t a r e p o t n e r r u c y l p p u s i p o 3 . 3 d d c l z h m 6 . 6 6 ; f p 0 =0 0 1 a m c l z h m 0 0 1 ; f p 0 =0 0 1 y c n e u q e r f t u p n if i v d d v 3 . 3 =2 16 1z h m e c n a t i c a p a c t u p n i ) 1 ( c n i s t u p n i c i g o l5 f p c x n i s n i p 2 x & 1 x7 25 4 e m i t n o i t i s n a r t ) 1 ( t s n a r t y c n e u q e r f t e g r a t % 1 o t g n i s s o r c t s r i f o t3 s m e m i t g n i l t t e s ) 1 ( t s y c n e u q e r f t e g r a t % 1 o t g n i s s o r c t s r i f m o r f2 n o i t a z i l i b a t s k c o l c ) 1 ( t b a t s v m o r f d d y c n e u q e r f t e g r a t % 1 o t v 3 . 3 =3 note: 1. guaranteed by design, not 100% tested in production. r e t e m a r a pl o b m y ss n o i t i d n o c. n i m. p y t. x a ms t i n u t n e r r u c y l p p u s g n i t a r e p oi p o 5 . 2 d d c l z h m 8 . 6 6 ; f p 0 =0 5 a m c l z h m 0 0 1 ; f p 0 =0 5 t n e r r u c n w o d r e w o pi p o 5 . 2 d d 0 0 1a w e k s ) 1 ( t ) 4 : 0 , f ( i c p _ u p c v t s d a e l u p c ; v 5 2 . 1 / v 5 . 1 =5 . 14 s n t ) f ( c i c p - ) e ( i c p v t v 5 . 1 =8 . 12 . 3 electrical characteristics - input/supply/common output parameters t a = 0c - 70c; supply voltage v dd = 3.3 v 5%, v ddl = 2.5v 5% (unless otherwise stated). stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings arestress specifications only and functional operation of the device at these or any other conditions above those listed in theoperational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periodsmay affect product reliability. absolute maximum ratings
PI6C106 pentium/pro tm system clock chip 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 6 ps8546a 07/13/01 r e t e m a r a pl o b m y ss n o i t i d n o c. n i m. p y t. x a ms t i n u e g a t l o v h g i h t u p t u ov h o i h o a m 2 1 ? =2 v e g a t l o v w o l t u p t u ov l o i l o a m 2 1 =4 . 0 t n e r r u c h g i h t u p t u oi h o v h o v 7 . 1 =6 1 ? a m t n e r r u c w o l t u p t u oi l o v l o v 7 . 0 =9 1 e m i t e s i rt r v l o v , v 4 . 0 = h o v 0 . 2 =6 . 1 s n e m i t l l a ft f v h o v , v 0 . 2 = l o v 4 . 0 =6 . 1 e l c y c y t u dd t v t v 5 2 . 1 =5 45 5% w e k st k s v t v 5 2 . 1 =5 7 1 s p t n e m e c a l p s i d e g d e e l g n i s , r e t t i j ) 2 ( t d e s j v t v 5 2 . 1 =0 5 2 a m g i s e n o , r e t t i jt 1 j v t v 5 2 . 1 =0 5 1 e t u l o s b a , r e t t i jt s b a j v t v 5 2 . 1 =0 0 3 ?0 0 3 electrical characteristics - cpu t a = 0c - 70c; v dd = 3.3v 5%, v ddl = 2.5v 5%; c l = 10-20pf (unless otherwise stated). notes: 1. guaranteed by design, not 100% tested in production. 2. edge displacement of a period relative to a 10-clock-cycle rolling average period r e t e m a r a pl o b m y ss n o i t i d n o c. n i m. p y t. x a ms t i n u e g a t l o v h g i h t u p t u ov 1 h o i h o a m 1 1 ? =6 . 2 v e g a t l o v w o l t u p t u ov 1 l o i l o a m 4 . 9 =4 . 0 t n e r r u c h g i h t u p t u oi 1 h o v h o v 0 . 2 =2 2 ? a m t n e r r u c w o l t u p t u oi 1 l o v l o v 8 . 0 =6 1 e m i t e s i rt r v l o v , v 4 . 0 = h o v 4 . 2 =2 s n e m i t l l a ft f v h o v , v 4 . 2 = l o v 4 . 0 =2 e l c y c y t u dd t v t v 5 . 1 =5 45 5% w e k st k s v t v 5 . 1 =0 0 5 s p t n e m e c a l p s i d e g d e e l g n i s , r e t t i j ) 2 ( t d e s j v t v 5 2 . 1 =0 0 5 e t u l o s b a , r e t t i jt s b a j v t v 5 . 1 =0 5 2 ?0 0 2 v t v 5 . 1 =0 5 2 electrical characteristics - pci t a = 0c - 70c; v dd = v ddl = 3.3v 10%, c l = 30pf (unless otherwise stated). notes: 1. guaranteed by design, not 100% tested in production.
PI6C106 pentium/pro tm system clock chip 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567890123 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567890123 7 ps8546a 07/13/01 r e t e m a r a pl o b m y ss n o i t i d n o c. n i m. p y t. x a ms t i n u e g a t l o v h g i h t u p t u ov h o i h o a m 2 1 ? =6 . 2 v e g a t l o v w o l t u p t u ov l o i l o a m 9 =4 . 0 t n e r r u c h g i h t u p t u oi h o v h o v 0 . 2 =2 2 ? a m t n e r r u c w o l t u p t u oi l o v l o v 8 . 0 =6 1 e m i t e s i rt r v l o v , v 4 . 0 = h o v 4 . 2 =2 s n e m i t l l a ft f ) 1 ( v h o v , v 4 . 2 = l o v 4 . 0 =2 e l c y c y t u dd t v t v 5 . 1 =3 55 5% , r e t t i ja m g i s e n ot s 1 j v t v 5 . 1 =3 s n e t u l o s b a , r e t t i jt s b a j v t v 5 . 1 =5 ?5 electrical characteristics - ref0 t a = 0c - 70c; v dd = v ddl = 3.3v 10%, c l = 50pf (unless otherwise stated). note: 1. guaranteed by design, not 100% tested in production. r e t e m a r a pl o b m y ss n o i t i d n o c. n i m. p y t. x a ms t i n u e g a t l o v h g i h t u p t u ov h o i h o a m 2 1 ? =0 . 2 v e g a t l o v w o l t u p t u ov l o i l o a m 2 1 =4 . 0 t n e r r u c h g i h t u p t u oi h o v h o v 7 . 1 =6 1 ? a m t n e r r u c w o l t u p t u oi l o v l o v 7 . 0 =9 1 e m i t e s i rt 2 r v l o v , v 4 . 0 = h o v 0 . 2 =6 . 1 s n e m i t l l a ft 2 f v h o v , v 0 . 2 = l o v 4 . 0 =6 . 1 e l c y c y t u dd 2 t v t v 5 2 . 1 =5 45 5% , r e t t i ja m g i s e n o ) 1 ( t s 1 j v t v 5 . 1 =3 s n e t u l o s b a , r e t t i j ) 1 ( t s b a j v t v 5 . 1 =6 ?6 electrical characteristics - ioapic t a = 0c - 70c; v dd = v ddl = 3.3v 10%, c l = 20pf (unless otherwise stated). r e t e m a r a pl o b m y ss n o i t i d n o c. n i m. p y t. x a ms t i n u e g a t l o v h g i h t u p t u ov h o i h o a m 1 1 ? =4 . 2 v e g a t l o v w o l t u p t u ov l o i l o a m 4 . 9 =4 . 0 t n e r r u c h g i h t u p t u oi h o v h o v 0 . 2 =8 1 ? a m t n e r r u c w o l t u p t u oi l o v l o v 8 . 0 =2 1 e m i t e s i rt r v l o v , v 4 . 0 = h o v 4 . 2 =5 . 2 s n e m i t l l a ft f v h o v , v 4 . 2 = l o v 4 . 0 =5 . 2 e l c y c y t u d ) 1 ( d t v t v 5 . 1 =5 45 5% , r e t t i ja m g i s e n o ) 1 ( t s 1 j v t v 5 . 1 =3 s n e t u l o s b a , r e t t i j ) 1 ( t s b a j v t v 5 . 1 =6 ?6 electrical characteristics - 48m t a = 0c - 70c; v dd = v ddl = 3.3v 5%, c l = 20pf (unless otherwise stated).
PI6C106 pentium/pro tm system clock chip 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 8 ps8546a 07/13/01 pericom semiconductor corporation 2380 bering drive ? san jose, ca 95131 ? 1-800-435-2336 ? fax (408) 435-1100 ? http://www.pericom.com 28-pin ssop package (h) ordering information . o n t r a pe g a k c a pn / p g n i r e d r o 6 0 1 c 6 i p) 8 2 - h ( p o s sh - 6 0 1 c 6 i p
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